The present invention generally relates to testing of integrated circuits (ICs) in scan designs. Particularly, the present invention relates to a method and device for coding test vectors for scan design.
Testing of integrated circuits (ICs) includes several components, which are part of a comprehensive test procedure, namely, “External Automatic Test Equipment” (ATE), “IC built-in self-test hardware” (BIST), and “Automatic Test Pattern Generation” (ATPG) software.
External Automatic Test Equipment stores test data and controls the ICs under test via a restricted number of Primary Inputs (PIs) for signal and data input, whereas IC built-in self-test hardware generates pseudo-random test vectors and response signatures. Automatic Test Pattern Generation (ATPG) software generates test data for Deterministic Stored Pattern Test (DSPT) and simulates test execution of both BIST and DSPT.
In order to reduce costs for expensive ATEs numerous BIST schemes have been proposed in recent years. They incorporate built-in features to apply test vectors to the tested circuit and to evaluate the resulting responses. A number of different methods to generate exhaustive, random, weighted random and deterministic test vectors have been developed. An ideal method should guarantee complete fault coverage, obtained with low hardware overhead and within short test application time.
Mixed-mode oriented testing exploits BIST and DSPT to achieve complete fault coverage. Pseudo-random vectors are applied to cover the easy-to-test faults, while deterministic vectors target the remaining hard-to-test faults. In the future the amount of memory required for explicitly storing deterministic test data will grow and may get too large for practical implementation. As a solution LFSR-Coding, also known as Re-Seeding, has been proposed to compress and decompress test data.
LFSR-Coding is characterized by the fact that expansion of compressed stored test data is done by a hardware structure already available for BIST. However, in order to meet both, fast BIST and efficient LFSR-Coding several refinements and extensions to the basic LBIST hardware have been proposed.
Rajski et al., 1995, IEEE, “Decompression of Test Data Using Variable-Length Seed LFSRs” proposes the use of Multiple Polynomial Linear Feedback Shift Register (MP-LFSR) to support LFSR-Coding in Variable-Length Seed.
U.S. Pat. No. 5,991,909 by Rajski et al., assigned to Mentor Graphics Corporation, Wilsonville, Oreg., US, filed, Oct. 15, 1996, issued Nov. 23, 1999, “Parallel Decompression And Related Methods And Apparatuses” describes parallel decompression using multiple scan chains and multiplexers to merge ATE stored data in pseudo-random vectors generation.
Könemann, 1991, ITL Munich, Germany, “LFSR-Coded Test Pattern for Scan-Design” discusses an alternative method for compact test data storage which achieves full test coverage, but is more compatible with system level Self-Test than with Weighted Random Pattern (WRP) test is. Intelligent, constructive Re-Seeding of a linear Pseudo Random Pattern Generator (PRPG) is used to manipulate the generated patterns as required for full fault testing. The required data storage volume, number of test pattern, test application time, and on-product hardware overhead for state-of-the art CMOS chip example is estimated based on theoretical considerations.
Considering current ATPG systems LFSR-Coding for such hardware structure are not yet supported or only with low efficiency. They basically consist of modules for deterministic and pseudo-random test vector generation for fault simulation and features to control the chip under test. A possibility for LFSR-Coding is to use common cycle simulation, but this method results in very low efficiency.